There exists, throughout the world, a wide variety of mains AC voltages. Broadly, there are two groups: those of the low voltage range (88 V-132 V) and those of the high voltage range (176 V-264 V). It is desirable to design electrically powered equipment which can be used throughout the world, thereby simplifying design and production and allowing equipment to be portable between countries other than where originally purchased. This requires that the equipment must be adaptable for use on both low and high voltage ranges. AC electrical power is distributed at frequencies of nominally 50 to 60 Hz, with a tolerance of 3 Hz typically allowed.
The requirement for a circuit to provide a substantially constant DC voltage when supplied with a range of AC input voltages is popularly fulfilled by the use of a doubler/bridge switch in association with an AC to DC converter circuit. Such a switch operates so as to select voltage doubling and rectification for AC inputs of the low voltage range and to select full wave bridge rectification for AC inputs of the high voltage range. Both manual and automatic types are known.
FIG. 1 shows a typical doubler/bridge arrangement for rectification and smoothing of input AC voltage V.sub.AC, diodes D.sub.1 to D.sub.4 forming a full-wave bridge rectifier, with AC input voltage V.sub.AC being applied between nodes 2, 3 and the rectified output available between nodes 4, 5. Capacitors C.sub.1 and C.sub.2 act to smooth the rectified output to a constant DC level, and switching element T permits the switching between full wave bridge rectification when in a non-conducting state, and voltage doubling rectification when in a conducting state. A load L may be connected between nodes 4, 5. When this circuit is used in voltage doubling rectifier mode, capacitor C.sub.1 is the positive half cycle smoothing capacitor, and capacitor C.sub.2 is the negative half cycle smoothing capacitor. In a manually controlled circuit, the switching element is a mechanical switch. In an automatic doubler/bridge circuit, the switching element T may be a relay, a triac or another equivalent device.
Once a triac is turned on by applying a bias voltage to its control terminal, it will then remain conductive until the current through it fails below the minimum holding current value, irrespective of the voltage applied to its control terminal. Hence, only a short pulse of bias voltage is required to turn on a triac, provided that the potential difference between its main terminals is greater than that required to cause the minimum holding current to flow.
Missing cycles are temporary blockages of the AC power, and are produced, for example, during changeover of the power supply between substations and feeder lines of the electricity supply company. As missing cycles represent periods of no mains supply, the voltage output of an AC/DC converter will drop as a result of the load draining charge from its output smoothing capacitors until resumption of AC supply.
Manually controlled doubler/bridge circuits require the operator of the electrical equipment to set the switch in the correct position before applying the AC mains supply.
The manually controlled doubler/bridge circuit has a major drawback in that the operator may forget to check the position or choose the wrong position of the switch, which could cause doubling of a high voltage, leading to damage to the equipment. Alternatively, the equipment could be designed to withstand such damage, leading to extra cost of the equipment.
Several types of automatic doubler/bridge switches are known, which automatically select voltage doubling and rectification of the input voltage when a 110 V line voltage is applied and select full wave rectification when a 220 V line voltage is applied. Examples of such circuits may be found described in U.S. Pat. Nos. 4,665,323; 4,845,607; 4,933,832 and British patent numbers 1,299,560; 2,144,931, 2,157,031. Such automatic switches may be constructed of discrete components, or constructed within an integrated circuit. Both the integrated type, and the type constructed with discrete components use a full-wave rectifier bridge, with a switching element and two capacitors, allowing both voltage doubling rectification and bridge rectification to be performed. The switching elements of the prior art are electrically operated mechanical switches (relays) or solid state bi-directional switches, for example triacs. The conducting state of such a triac is controlled by the presence or absence of a bias voltage applied to its control gate, such voltage being supplied by an automatic circuit as a function of the voltage applied to the equipment. The known designs of automatic doubler/bridge switch usually produce either a continuous bias voltage or a continuous series of firing pulses to the gate of triac T. Whilst this ensures immediate recovery of output voltage following a missing cycle, an unacceptably large power consumption results. In some circuits, up to 12 W of power may be consumed by the control circuitry, and 80% of this in triac gate firing pulses.
Equally, a manually controlled circuit could use a triac or equivalent as the switching element T with a manual switch controlling the presence or absence of a bias voltage to the triac control terminal.
When such an automatic doubler/bridge circuit operates in voltage doubling rectifier mode under constant AC supply, the triac switching element T conducts from the moment a firing pulse is provided by the control circuit until the current through its main terminals falls below the holding current. During a positive half cycle, current flows through diode D.sub.1 to charge the positive half cycle smoothing capacitor C.sub.1 while the input AC voltage V.sub.AC is higher than the voltage across the terminals of that capacitor. The capacitor charges up through the triac until the point of maximum charge, usually just after the peak value of the input AC voltage. At this point, the capacitor charging current ceases as the input AC voltage V.sub.AC drops, and the triac turns off. Similarly, during a negative half cycle, current flows through diode D.sub.2 to charge the negative half cycle smoothing capacitor C.sub.2 until its point of maximum charge, just after the peak negative input voltage of the AC mains. In this way, the voltage across each one of capacitors C.sub.1, C.sub.2 is almost equal to the peak AC mains input voltage, and the total DC voltage available at the output terminals 4, 5 for application to load L is approximately double the peak AC input voltage. The diodes D.sub.1, D.sub.2 are reverse biased after the AC input voltage has dropped below the voltage across the terminal of the capacitor and hence the charge stored on capacitors C.sub.1, C.sub.2 is prevented from discharging through them.
When a load L is connected to terminals 4, 5 the capacitors discharge through the load and supply it with the required DC current. This discharging causes the voltage across the capacitors C.sub.1, C.sub.2 to decrease, until each one is charged during the following positive or negative mains half cycle, respectively. This discharging and charging causes a ripple voltage on the DC output voltage. The size of the capacitors C.sub.1, C.sub.2 is chosen so that the charge stored smoothes the DC output voltage to have an acceptable level of ripple.
One integrated circuit implementation described in U.S. Pat. No. 5,162,984 has particular advantages due to its small size and extremely low power consumption. Triac firing pulses are produced only during a limited time period soon after zero crossing points of the AC voltage, thus ensuring efficient triac turn-on, whilst the current consumption by the triac firing pulses is minimised. It has become a popular circuit for AC to DC conversion.
FIG. 2 shows a circuit incorporating such an automatic doubler/bridge control circuit. AC mains input voltage V.sub.LN is applied to power supply lines V.sub.L, V.sub.N connected to nodes 2, 3 of the bridge rectifier formed by diodes D.sub.1 -D.sub.4. An integrated circuit automatic doubler/bridge control circuit 7 is connected to the neutral mains input line V.sub.N, which may be regarded as a supply voltage. The doubler/bridge control circuit 7 is further connected to node 9, which may be regarded as a virtual ground voltage for the IC supply. Node 9 is itself connected by capacitor 11 to the neutral AC input line V.sub.N, and to the live AC input line V.sub.L by a series arrangement of a resistor 13 and a diode 15. Two series connected resistors 17, 19, are connected between the node 9 and the live mains input line V.sub.L, the node 21 between the resistors 17,19 being connected to control circuit 7. A resistor 23 is connected between the node 21 and the neutral mains input line V.sub.N. An output of the control circuit 7 is connected to the gate of the triac switching element T through a current limiting resistor 25.
The half wave rectifier comprising diode 15, resistor 13 and capacitor 11 provides a DC supply voltage V.sub.c to the control circuit 7. This supply is typically 9 V lower than the voltage of the neutral mains supply line V.sub.N, regulated by a voltage regulator internal to the control circuit 7.
Resistors 17, 19, 23 scale down and bias the AC input voltage V.sub.LN to a voltage at node 21 which is used by the control circuit 7 to produce triac firing pulses to triac T just after every mains zero crossing point if a low range AC voltage is in use (i.e. if voltage doubling rectifier mode is required). The control circuit 7 generates and uses internally: a signal RI, being the output of a voltage comparator, which indicates whether the AC supply voltage falls within a first, high range of supply voltages Rge1, or whether the AC mains lies within a second, low range of supply voltages Rge2; a clock signal Ck; and a zero cross detection signal T1 is a short active high pulse generated in response to each zero crossing of AC supply.
FIGS. 3A to 3F show a typical timing relationship for the operation of such a known automatic doubler/bridge circuit operating in voltage doubling rectifier mode during a period of constant AC supply, with the load L connected to the DC output. In FIG. 3A, V.sub.LN represents the input AC voltage; in FIG. 3B, V.sub.G T represents the triac gate voltage; in FIG. 3C, V.sub.C1 represents the voltages across the terminals of capacitor C.sub.1 and V.sub.CO1 represents the open circuit voltage which would appear across terminals 4, 6 in the absence of the load and the capacitor C.sub.1, with the triac becoming conductive at the first triac pulse after zero crossing; in FIG. 3D, I.sub.T represents the current flowing through the main terminals of the triac T; in FIG. 3E, V.sub.C2 represents the voltages at the terminals of capacitor C.sub.2 and V.sub.CO2 represents the open circuit voltage which would appear across terminals 5, 6 in the absence of the load and the capacitor C.sub.2, with the triac becoming conductive at the first triac pulse after zero crossing; and in FIG. 3F, (V.sub.C1 +V.sub.C2) represents the total DC output voltage between terminals 4, 5.
In FIGS. 3C, 3E, the dashed lines representing the open circuit voltages V.sub.CO1, V.sub.CO2 represent the maximum possible voltage which could be applied to the capacitors C.sub.1, C.sub.2 at any particular instant.
The AC input waveform V.sub.LN crosses the zero voltage level at zero crossing points t.sub.c0 -t.sub.c3.
As shown in FIG. 3B, a short time d.sub.t after each zero crossing, at times t.sub.d0 -t.sub.d3, a series of pulses lasting for a period d.sub.p are produced on the triac gate voltage V.sub.G T. These triac firing pulses are active-LOW; during the active state the triac gate terminal is held at the voltage of the virtual ground, node 9 in FIG. 2 and at other times the triac gate is held at the voltage of the neutral line, V.sub.N and node 3 in FIG. 2. The timing of these triac gate pulses is designed to allow the triac to be conductive as soon as possible after the voltage across the triac is sufficient to maintain a holding current. This corresponds to times t.sub.i0 -t.sub.i3 in FIG. 3C, when the voltage available to charge the capacitor V.sub.CO1 first exceeds the voltage V.sub.C1 across capacitor C.sub.1 sufficiently to hold the triac on. Times t.sub.i0 -t.sub.i3 vary in their temporal location as the load current supplied by the circuit, and hence the ripple voltage, varies. An increased load will mean a greater capacitor discharge between charging half cycles and hence an increased ripple voltage and an earlier location of time t.sub.i0. A sequence of triac gate firing pulses is required to ensure that the triac is turned on as early as possible, independently of the ripple voltage at any particular instant, but the duration d.sub.p of the series of pulses should be no longer than necessary, to avoid excessive current consumption.
Considering only the first half cycle of mains, between times t.sub.c0 and t.sub.c1, as shown in FIG. 3D, the triac beans to conduct current I.sub.T at time t.sub.i0, which charges capacitor C.sub.1. With the triac conductive, the full AC supply is applied across capacitor C.sub.1. In the periods d.sub.t between the zero crossing points t.sub.c0 -t.sub.c3 and the associated triac turn on time t.sub.i0 -t.sub.i3 the rectifier circuit is operating in bridge rectifier mode and the input AC voltage is applied across the series combination of both capacitors.
The terminal voltage V.sub.C1 across the capacitor C.sub.1 rises, as shown in FIG. 3C. The open circuit voltage available V.sub.CO1 exceeds the capacitor terminal voltage V.sub.C1 during this period, due to resistive losses caused by the current flowing to the load L and the current charging the capacitor.
After reaching its peak value, the mains voltage falls and a time t.sub.X0 is reached, soon after the peak voltage of AC mains, where difference between the capacitor terminal voltage V.sub.C1 and the voltage available V.sub.CO1 is less than the voltage required to maintain the minimum holding current through the triac. At this time, t.sub.X0, the triac turns off and the current I.sub.T through the triac falls to zero (FIG. 3D). At this time, t.sub.X0, the capacitor C.sub.1 is charged to a voltage almost equal to the peak value of AC mains input voltage.
For the remainder of this half cycle, from time t.sub.X0 to time t.sub.i2, diodes D.sub.1 and D.sub.3 are reverse biased and the charge on the capacitor discharges through the load L. This causes the capacitor terminal voltage V.sub.C1 to drop during this period (FIG. 3C).
Symmetry of the circuit and the AC mains applied dictates identical operation during the negative half cycle, from time t.sub.C1 to time t.sub.C2. Zero crossing at time t.sub.C1 causes a series of triac firing pulses starting at time t.sub.d1, for a period of d.sub.p. Capacitor C.sub.2 is charged through diode D.sub.2 and triac T, between times t.sub.i1 and t.sub.X1. The charge stored discharges through the load between times t.sub.X1 and t.sub.i3. The capacitor terminal voltage V.sub.C2 will drop, shown in FIG. 3E, during this period by an amount which depends on the current demand of the load, and the size of capacitor C.sub.2.
FIG. 3F shows the output voltage, which is supplied across both capacitors C.sub.1 and C.sub.2, achieving a DC output voltage (V.sub.C1 +V.sub.C2) approximately double the AC input voltage. The voltage drop of each capacitor's terminal voltage gives rise to a ripple voltage Vr in the DC output voltage (V.sub.C1 +V.sub.C2), at double the frequency of the AC input. For any given load requirement, the size of the capacitors C.sub.1 and C.sub.2 is chosen to reduce this ripple voltage Vr to a tolerable magnitude.
The voltage waveforms V.sub.C1, V.sub.C2 across the output capacitors C.sub.1, C.sub.2 respectively are identical to those resulting from the use of a conventional voltage doubling circuit with an electrical connection in the place of the triac T.
The remaining ripple voltage V.sub.r in the output voltage (V.sub.C1 +V.sub.C2), exaggerated for clarity in the diagrams, depends on the mount of discharge the capacitors C.sub.1 and C.sub.2 undergo during the period between triac turn-on times t.sub.i0 -t.sub.i3 and hence the loading applied to the output. The maximum output level V.sub.DC P of DC Output voltage (V.sub.C1 +V.sub.C2) is obtained at each triac turn-off time t.sub.X0 -t.sub.X3. This level will be used as a reference below.
During a missing cycle, the voltage V.sub.LN will be held at the voltage of the AC mains input when the power interruption started, by the capacitance of a mains filter habitually connected across the input mains terminals of switched mode power supplies and the like, to prevent incoming or outgoing noise on the AC supply line, or the capacitance of the AC line and circuit itself, decaying towards zero as the capacitance discharges.
The automatic integrated doubler/bridge switching circuit described in U.S. Pat. No. 5,162,984 works well with a constant sinusoidal AC supply voltage but suffers when missing cycles occur on the mains input.
This circuit reacts in two very different ways to missing cycles of AC mains, depending on whether the mains input recovers with the same or the opposite polarity to that which it had at the interruption of power.
FIGS. 4A-4E show timing relationships for the operation of a known automatic doubler/bridge circuit in voltage doubling rectifier mode during and after a missing cycle of power supply which recovers with the opposite polarity to that when the interruption started. Features identical to those in FIGS. 3A-3E have identical reference symbols.
At time t.sub.ms, the AC supply V.sub.LN is interrupted, shown in FIG. 4A; it returns with the opposite polarity at time t.sub.mf, rather less than one period later. During the missing cycle between times t.sub.ms and t.sub.mf, the capacitors C.sub.1, C.sub.2 discharge through the applied load and so the output voltage (V.sub.C1 +V.sub.C2) drops. The rate of voltage decay depends on the current demand of the applied load and the size of capacitors C.sub.1, C.sub.2. Due to the lack of input power, the current I,.sub.T through the triac, shown in FIG. 4D, fails below its holding current and it turns off at time t.sub.ms. When the power returns at time t.sub.mf, the AC supply voltage which has been held above zero by inherent capacitance in the mains supply system and the electrical apparatus containing the circuit crosses the zero voltage line to attain the polarity of the recovered AC input. The control circuit interprets this as a standard zero crossing detection, and initiates triac firing pulses a delay d.sub.t later, at time t'.sub.d1, as after a normal zero crossing point. This initiates triac conduction, FIG. 4D, and further charging of the capacitor C.sub.2, raising the capacitor's terminal voltage V.sub.C2, FIG. 4E, and the DC output voltage, FIG. 4F. Voltage doubling mode thus recommences very soon after the recovery of the AC mains, and full DC output voltage is achieved at time t.sub.R, during the second full half cycle after AC supply recovery time t.sub.mf. The maximum reduction in output voltage dV.sub.DC below the reference value V.sub.DC P is minimised by the fact that the input voltage resumption at time t.sub.mf instantly causes a zero crossing, and resumption of voltage doubling mode. The triac firing pulses generated after the resumption of power at time t.sub.mf are stopped if a further zero crossing t.sub.c2 occurs before the triac firing pulse generation period d.sub.p has elapsed. After the next zero crossing time t.sub.c2, normal operation resumes with the generation of triac firing pulses at time t.sub.d2.
FIGS. 5A-5F show analogous timing relationships for the operation of such an automatic doubler/bridge circuit operating in voltage doubling rectifier mode during and after a missing cycle which recovers with the same polarity as that when interrupted. Features identical to those in FIGS. 3A-3F have identical reference symbols.
At time t.sub.ms, the AC supply V.sub.LN is interrupted; it returns wkh the same polarity at time t.sub.mf, somewhat less than one period later. During this missing cycle the capacitors C.sub.1, C.sub.2 discharge through the applied load and so the output voltages V.sub.C1, V.sub.C2 drop. The rate of voltage decay depends on the current demand of the applied load L. At the time of power interruption t.sub.ms, the current I.sub.T through the triac stops and the triac turns off.
When the power returns at time t.sub.mf, the circuit is in bridge rectifier mode, as the triac is turned off. For the remaining part of the half cycle until time t.sub.c2, there are no valid zero crossings to initiate triac firing pulses and hence triac conduction and voltage doubling. Following the resumption of power at time t.sub.mf, the voltage V.sub.OC1 available to capacitor C.sub.1 is half that which it would have been without a missing cycle, the other half of the voltage also being available to capacitor C.sub.2. This may help the recovery of DC output voltage (V.sub.C1 +V.sub.C2), FIG. 5F, (depending on the state of discharge of the capacitors C.sub.1, C.sub.2) but the DC output voltage remains much reduced. Following the next valid zero cross at time t.sub.c2, the next triac firing pulse series begins at time t.sub.d2, and voltage doubling rectifier mode is resumed. As shown in FIG. 5F, the DC output voltage (V.sub.C1 +V.sub.C2) is reduced from the time of the power interruption t.sub.ms until the second full half cycle after power resumption (one of each polarity), even though full power has been available since the resumption of power at time t.sub.mf. The output voltage drop dV.sub.DC is greater than that in the case of power resumption with opposite polarity, FIG. 4F. This reduction in output voltage dV.sub.DC can be significant when moderate to heavy loads are applied to the output DC supply. This voltage drop can impair the functioning of computers and video equipment by causing loss of stored data and faulty video signals.